Trench capacitors are widely used in Dynamic Random Access Memory (DRAM) devices for data storage. A trench DRAM cell consists of a trench capacitor and a transistor. The trench capacitor typically consists of a hole etched into the substrate, a first electrode—often referred as a “buried plate”—in the substrate, a second electrode in the trench, and a thin storage-node dielectric which separates those two electrodes. The transistor is formed above the trench capacitor. A dielectric isolation collar is formed in the upper region of the trench to suppress undesired parasitic leakage current between the transistor and the capacitor.
A buried plate is formed in the substrate adjacent the trench by out-diffusing a dopant such as arsenic (As) into the substrate. Buried plate doping may be formed by conventional solid phase doping processes such as out-diffusing arsenic from a layer of arsenic-doped silicon glass (ASG) on trench sidewall, liquid phase doping, gas phase doping (GPD), plasma doping, plasma immersion ion implantation, infusion doping, or any combination of these methods that are well known in prior art. Trench capacitance enhancement may be optionally practiced before or after buried plate formation. The trench enhancement approaches may include forming a bottle-shape in the lower trench, roughening the lower trench by forming hemispherical silicon grains on the lower trench surface, or any other trench capacitance enhancement methods known in prior art. See, for example, U.S. Pat. Nos. 6,544,838; 6,495,411; 6,403,412; 6,190,988; 5,849,638; 6,448,131; and 6,555,430, all of which are included in their entireties herein by reference, for methods of enhancing trench surface and thus trench capacitance.
A bottle-shaped trench is formed by widening the dimensions of the bottom portion of the trench to form a bottle-shaped trench. The capacitance of a trench capacitor, to be formed thereafter along the bottom portion of the trench, is enhanced when the bottom portion is widened. Methods for forming a bottle-shaped trench are well known in the art. See, for example, U.S. Pat. Nos. 5,891,807; 6,190,988; 6,232,171; 6,403,412; and 6,544,838, all of which are included in their entireties herein by reference.
The node dielectric may be any suitable dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, combinations of these dielectric materials, or another high-k material. The node dielectric may be formed by any suitable process, including but not limited to, chemical vapor deposition (CVD), thermal oxidation, thermal nitridation, atomic layer deposition (ALD). For example, the node dielectric layer may comprise silicon nitride formed by LPCVD followed by a high temperature anneal (e.g., 800-1100° C.) in an environment containing oxygen.
The capacitor electrode in the trench usually consists of heavily doped polycrystalline silicon (polysilicon). The isolation collar process, which usually comprises a high-temperature oxidation step, is generally performed after the trench is filled with heavily doped polysilicon and the polysilicon is recessed to a predetermined depth.
During the high-temperature isolation collar process of forming a trench capacitor, the upper trench sidewall is exposed to the heavily doped polysilicon residing in the lower trench. Dopants are driven out from the heavily doped polysilicon in the lower trench. Some dopants diffuse into the substrate where the isolation collar is formed, causing undesirable doping in the substrate next to the isolation collar, referred to as auto-doping. Auto-doping increases parasitic leakage current and thus degrades the device characteristics.
Therefore, it is desired to have a structure and a process for forming a trench capacitor without suffering from the auto-doping problem.